SDRAM Memory Controller IP

The memory controller IP core interfaces to standard SDRAM technology, capable of being configured for multiple data path widths (8, 16, 32, 64, 72).

Two options are available for the user interface to the memory controller: 1. a lower level interface to more tightly control access, such as read and write counts; 2. a higher level interface using a linear address bus with control lines and data bus. The high level interface allows for quick integration into projects but may increase access latency. The low level interface can speed up transfers to and from the SDRAM if information, such as transfer size, is known in advance by the interface.


  • Programmable CAS latency
  • Burst termination
  • Bank management to minimize ACTIVE commands
  • Supports all standard SDRAM commands
  • Data mask signals for byte lane control
  • Programmable timing parameters
  • Optional SPD interface and parameter configuration for DIMMs.
  • Multiple DIMM support